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ltc3565 1 3565fb features applications description 1.25a, 4mhz, synchronous step-down dc/dc converter the ltc ? 3565 is a constant frequency, synchronous step-down dc/dc converter. intended for medium power applications, it operates from a 2.5v to 5.5v input voltage range and has a user-con? gurable operating frequency up to 4mhz, allowing the use of tiny, low cost capacitors and inductors 1mm or less in height. the output voltage is adjustable from 0.6v to 5.5v. internal synchronous power switches provide high ef? ciency. the ltc3565s current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. the ltc3565 can be con? gured for automatic power saving burst mode operation (i q = 40a) to reduce gate charge losses when the load current drops below the level required for continuous operation. for reduced noise and rf interference, the sync/mode pin can be con? gured to skip pulses or provide forced continuous operation. to further maximize battery life, the p-channel mosfet is turned on continuously in dropout (100% duty cycle). in shutdown, the device draws <1a. l , lt, ltc, ltm, linear technology the linear logo, burst mode and opti-loop are registered trademarks of linear technology corporation. hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6498466, 6611131. step-down 2.5v/1.25a regulator n high ef? ciency: up to 95% n v in range: 2.5v to 5.5v n high frequency operation: up to 4mhz n selectable low ripple (typical 25mv p-p ) burst mode ? operation: i q = 40a n stable with ceramic capacitors n uses tiny capacitors and inductor n low r ds(on) internal switches: 0.15 n current mode operation for excellent line and load transient response n short-circuit protected n low dropout operation: 100% duty cycle n low shutdown current: i q 1a n output voltages from 0.6v to 5v n synchronizable to external clock n supports pre-biased outputs n small 10-lead (3mm 3mm) dfn or msop package n notebook computers n digital cameras n cellular phones n handheld instruments n board mounted power supplies sync/mode ltc3565 pv in sw sv in run pgood ith rt gnd v fb 2.2h v out 2.5v 1.25a v in 2.5v to 5.5v 22pf 931k 294k 680pf 3565 ta01a 22f 12.1k 22f 191k output current (ma) 0.1 1 10 0 efficiency (%) power loss (w) 40 30 100 1 0.1 0.01 0.001 0.0001 1000 100 10000 3565 ta01b 20 10 60 50 80 70 90 v in = 2.7v v in = 3.6v v in = 4.2v ef? ciency and power loss vs output current typical application
ltc3565 2 3565fb pin configuration electrical characteristics absolute maximum ratings pv in , sv in voltages .................................... C0.3v to 6v v fb , ith voltages ......................... C0.3v to (v in + 0.3v) sync/mode, pgood voltage ..... C0.3v to (v in + 0.3v) sw voltage (dc) .......................... C0.3v to (v in + 0.3v) run voltage ................................................ C0.3v to 6v (note 1) symbol parameter conditions min typ max units v in operating voltage range 2.5 5.5 v i fb feedback pin input current (note 3) 50 na v fb feedback voltage (note 3) l 0.588 0.6 0.612 v v linereg reference voltage line regulation v in = 2.5v to 5.5v 0.04 0.2 %/v v loadreg output voltage load regulation ith = 0.55v to 0.9v l 0.02 0.2 % g m(ea) error ampli? er transconductance ith pin load = 5a (note 3) 300 s top view 11 gnd dd package 10-lead ( 3mm 3mm ) plastic dfn 10 9 6 7 8 4 5 3 2 1 ith v fb pgood sv in pv in rt run sync/mode sw gnd t jmax = 125c, ja = 43c/w, jc = 7.5c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 rt run sync/mode sw gnd 10 9 8 7 6 ith v fb pgood sv in pv in top view mse package 10-lead plastic msop 11 gnd t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad (pin 11) is gnd, must be soldered to pcb the denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t j = 25c. v in = 3.6v, r t = 125k unless otherwise speci? ed. (note 2) operating junction temperature range (notes 2, 5, 8) ........................................ C40c to 125c storage temperature range .................. C65c to 125c lead temperature (soldering, 10 sec) ................... 300c order information lead free finish tape and reel part marking* package description temperature range ltc3565edd#pbf ltc3565edd#trpbf ldnr 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3565idd#pbf ltc3565idd#trpbf ldnr 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3565emse#pbf ltc3565emse#trpbf ltdvj 10-lead plastic msop C40c to 125c ltc3565imse#pbf ltc3565imse#trpbf ltdvj 10-lead plastic msop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www .linear.com/tapeandreel/
ltc3565 3 3565fb electrical characteristics the denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t j = 25c. v in = 3.6v, r t = 125k unless otherwise speci? ed. (note 2) symbol parameter conditions min typ max units i s input dc supply current (note 4) active mode sleep mode shutdown v sync/mode = 3.6v, v fb = 0.55v v sync/mode = 3.6v, v fb = 0.8v v run = 0v 330 40 0.1 450 60 1 a a a f osc oscillator frequency rt = 125k (note 7) 1.3 1.5 1.7 4 mhz mhz f sync synchronization frequency (note 7) 0.4 4 mhz i lim peak switch current limit v in = 3v, v fb = 0.5v 1.5 2.1 2.5 a r ds(on) top switch on-resistance mse package dd package (note 6) 0.15 0.15 0.2 bottom switch on-resistance mse package dd package (note 6) 0.13 0.13 0.18 i sw(lkg) switch leakage current v in = 5.5v, v run = 0v, v fb = 0v 0.01 1 a v run run threshold l 0.3 0.8 1.5 v i run run leakage current l 0.01 1 a v uvlo undervoltage lockout threshold v in ramping down 1.9 2.2 v pgood power good threshold v fb ramping up from 0.45v to 0.6v v fb ramping down from 0.69v to 0.6v C7 7 % % r pgood power good pull-down on-resistance 15 20 pgood blanking v fb step from 0v to 0.6v v fb step from 0.6v to 0v 40 105 s s v sync-mode pulse skip force continuous burst 1.1 v in C 0.75 0.63 v in C 1.05 v v v t soft-start 10% to 90% of regulation 0.6 0.9 1.2 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3565 is tested under pulsed load conditions such that t j t a . the ltc3565e is guaranteed to meet performance speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3565i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these speci? cations is determined by speci? c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the ltc3565 is tested in a feedback loop which servos v fb to the midpoint for the error ampli? er (v ith = 0.7v). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient t a and power dissipation p d according to the following formulas: ltc3565edd: t j = t a + (p d ? 43c/w) ltc3565emse: t j = t a + (p d ? 40c/w) note 6: switch on-resistance is guaranteed by correlation to wafer level measurements and assured by design characterization and correlation with statistical process controls. note 7: 4mhz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see applications information). note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
ltc3565 4 3565fb ef? ciency vs output current ef? ciency vs frequency load regulation line regulation reference voltage vs temperature frequency variation vs temperature output current (ma) 0.1 1 10 0 efficiency (%) 40 30 100 1000 100 10000 3565 g04 20 10 60 50 80 70 90 v out = 1.8v burst mode operation forced continuous pulse skip frequency (mhz) 95 94 93 92 91 90 89 88 3565 g05 035 12 4 efficiency (%) v out = 1.8v 4.7h 1h 2.2h input voltage(v) 0.6 0.4 0.2 0.0 C0.2 C0.4 C0.6 3565 g07 2.5 4.0 5.0 5.5 3.0 3.5 4.5 v out error (%) v out = 1.8v i load = 400ma temperature(c) 6 4 2 0 C2 C4 C6 3565 g09 C50 25 75 100 125 C25 0 50 frequency variation (%) output current(ma) 1.00 0.75 0.50 0.25 0.00 C0.25 C0.50 3565 g06 0 600 1000 1200 1400 200 400 800 v out error (%) v out = 1.8v forced continuous burst mode operation pulse skip temperature (c) C50 reference voltage (mv) 605 610 615 25 75 3565 g08 600 595 C25 0 50 100 125 590 585 typical performance characteristics ef? ciency vs input voltage ef? ciency vs output current ef? ciency vs output current t j = 25c, v in = 3.6v, f o = 1mhz, unless otherwise noted. input voltage(v) 2.5 100 90 80 70 60 50 40 30 4.0 5.0 3565 g01 3.0 3.5 4.5 5.5 efficiency (%) i out = 100ma i out = 1.25a v out = 1.8v i out = 1ma i out = 0.1ma i out = 10ma output current (ma) 0.1 1 10 0 efficiency (%) 40 30 100 1000 100 10000 3565 g02 20 10 60 50 80 70 90 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.8v output current (ma) 0.1 1 10 0 efficiency (%) 40 30 100 1000 100 10000 3565 g03 20 10 60 50 80 70 90 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.5v
ltc3565 5 3565fb frequency variation vs input voltage r ds(on) vs input voltage r ds(on) vs temperature input voltage (v) 6 4 2 0 C2 C4 C6 C8 3565 g10 2.5 4.0 5.0 5.5 3.0 3.5 4.5 frequency variation (%) input voltage (v) 0.25 0.20 0.15 0.10 0.05 0.0 3565 g11 2.5 4.0 5.0 5.5 3.0 3.5 4.5 r ds(on) () main switch synchronous switch temperature (c) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 3565 g12 C50 25 75 100 125 C25 0 50 r ds(on) () main switch synchronous switch typical performance characteristics t j = 25c, v in = 3.6v, f o = 1mhz, unless otherwise noted. dynamic supply current vs input voltage dynamic supply current vs temperature input voltage (v) 0.001 3.0 3.5 4.0 4.5 5.0 5.5 2.5 dynamic supply current (ma) 0.1 100 3565 g13 0.01 1 10 forced continuous pulse skip burst mode operation v out = 1.8v i load = 0a temperature (c) 0.001 C25 0 25 50 75 100 125 C50 dynamic supply current (ma) 0.1 100 3565 g14 0.01 1 10 forced continuous pulse skip burst mode operation v out = 1.8v i load = 0a input voltage (v) 2500 2000 1500 1000 500 0 3565 g15 035 6 12 4 switch leakage (pa) synchronous switch main switch switch leakage vs input voltage temperature (c) 600 500 400 300 200 100 0 3565 g16 C50 25 75 100 125 C25 0 50 switch leakage (na) main switch synchronous switch v in = 3.6v v out = 1.8v i load = 50ma sw 2v/div v out 50mv/div ac coupled i l 200ma/div 3565 g17 4s/div v in = 3.6v v out = 1.8v i load = 5ma sw 2v/div v out 50mv/div ac coupled i l 200ma/div 3565 g18 4s/div switch leakage vs temperature burst mode operation pulse skipping mode
ltc3565 6 3565fb typical performance characteristics t j = 25c, v in = 3.6v, f o = 1mhz, unless otherwise noted. v in = 3.6v prebiased v out = 3v, v out = 1.8v i load = 0a v out 1v/div i l 500ma/div 3565 g22 200s/div v in = 3.6v v out = 1.8v i load = 0a to 1.25a burst mode operation v out 100mv/div ac coupled i l 1a/div i load 1a/div 3565 g23 40s/div v in = 3.6v v out = 1.8v i load = 50ma to 1.25a burst mode operation v out 100mv/div ac coupled i l 1a/div i load 1a/div 3565 g24 40s/div v in = 3.6v v out = 1.8v i load = 250ma to 1.25a burst mode operation v out 100mv/div ac coupled i l 1a/div i load 1a/div 3565 g25 40s/div v in = 3.6v v out = 1.8v i load = 0a v out 1v/div i l 2a/div 3565 g26 40s/div v in = 3.6v v out = 1.8v i load = 0a v out 1v/div i l 500ma/div 3565 g27 40s/div start-up from shutdown with a prebiased output (forced continuous mode) load step load step load step v out short to ground v out short to v in (forced continuous mode) v in = 3.6v v out = 1.8v i load = 80ma sw 2v/div v out 50mv/div ac coupled i l 200ma/div 3565 g19 2s/div v in = 3.6v v out = 1.8v i load = 0a burst mode operation run 2v/div v out 1v/div i l 500ma/div 3565 g20 400s/div v in = 3.6v v out = 1.8v i load = 1.25a burst mode operation run 2v/div v out 1v/div i l 1a/div 3565 g21 400s/div forced continuous mode start-up from shutdown start-up from shutdown
ltc3565 7 3565fb rt (pin 1): timing resistor pin. the oscillator frequency is programmed by connecting a resistor from this pin to ground. run (pin 2): converter enable pin. forcing this pin above 1.5v enables this part, while forcing it below 0.3v causes the device to shut down. in shutdown, the device draws <1a supply current. this pin must be driven; do not ? oat. sync/mode (pin 3): combination mode selection and oscillator synchronization pin. this pin controls the operation of the device. when tied to sv in or gnd, burst mode operation or pulse skipping mode is selected, respectively. if this pin is held at half of sv in , the forced continuous mode is selected. the oscillation frequency can be synchronized to an external oscillator applied to this pin. when synchronized to an external clock, pulse skip mode is selected. sw (pin 4): the switch node connection to the inductor. this pin swings from pv in to gnd. pin functions gnd (pin 5, exposed pad pin 11): main power ground pin. connect to the (C) terminal of c out , and (C) terminal of c in . the exposed pad must be soldered to electrical ground on the pcb. pv in (pin 6): main supply pin. must be closely decoupled to gnd. sv in (pin 7): the signal power pin. all active circuitry is powered from this pin. must be closely decoupled to gnd. sv in must be greater than or equal to pv in . pgood (pin 8): the power good pin. this common drain logic output is pulled to gnd when the output voltage is not within 7% of regulation. v fb (pin 9): receives the feedback voltage from the ex- ternal resistive divider across the output. nominal voltage for this pin is 0.6v. ith (pin 10): error ampli? er compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0.4v to 1.4v. nominal (v) absolute max (v) pin name description min typ max min max 1 rt timing resistor C0.3 0.4 sv in C0.3 sv in + 0.3 2 run enable pin C0.3 sv in C0.3 sv in 3 sync/mode m ode select/synchronization pin 0 sv in C0.3 sv in + 0.3 4 sw switch node 0 pv in C0.3 pv in + 0.3 5 gnd main power ground 0 6pv in main power supply C0.3 5.5 C0.3 6 7sv in signal power supply 2.5 5.5 C0.3 6 8 pgood power good pin 0 sv in C0.3 sv in + 0.3 9v fb output feedback pin 0 0.8 1.0 C0.3 sv in + 0.3 10 ith error ampli? er compensation 0 1.5 C0.3 sv in + 0.3
ltc3565 8 3565fb block diagram C + 8 9 C + + C C + 0.642v 0.6v error amplifier v b burst comparator bclamp nmos comparator pmos current comparator reverse comparator 0.558v 5 sw 4 pgood 10 ith v fb 1 rt 2 run 3 sync/mode 3565 bd 6 pv in 5 gnd 7 sv in slope compensation voltage reference oscillator logic ith limit C + C + + C gnd
ltc3565 9 3565fb operation the ltc3565 uses a constant frequency, current mode architecture. the operating frequency is determined by the value of the r t resistor or can be synchronized to an external oscillator. to suit a variety of applications, the selectable mode pin allows the user to trade-off noise for ef? ciency. the output voltage is set by an external divider returned to the v fb pin. an error ampli? er compares the divided output voltage with the reference voltage of 0.6v and ad- justs the peak inductor current accordingly. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage is not within 7% of its regulated value. a tripping delay of 40s and untripping delay of 105s ensures pgood will not glitch due to transient spikes on v out . main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle. current ? ows through this switch into the inductor and the load, increasing until the peak inductor current reaches the limit set by the voltage on the ith pin. then, the top switch is turned off, the bottom switch is turned on, and the energy stored in the inductor forces the current to ? ow through the bottom switch and the inductor out into the load until the next clock cycle. the peak inductor current is controlled by the voltage on the ith pin, which is the output of the error ampli? er. the output is developed by the error ampli? er comparing the feedback voltage, v fb , to the 0.6v reference voltage. when the load current increases, the output voltage and v fb decrease slightly. this decrease in v fb causes the er- ror ampli? er to increase the ith voltage until the average inductor current matches the new load current. the main control loop is shut down by grounding the run pin, resetting the internal soft-start. re-enabling the main control loop by pulling run high activates the internal soft-start, which slowly ramps the output voltage over approximately 0.9ms until it reaches regulation. low current operation three modes are available to control the operation of the ltc3565 at low currents. all three modes automatically switch from continuous operation to the selected mode when the load current is low. to optimize ef? ciency, the burst mode operation can be selected. when the load is relatively light, the ltc3565 automatically switches into burst mode operation in which the pmos switch operates intermittently based on load demand. by running cycles periodically, the switching losses which are dominated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. the burst comparator trips when ith is below approximately 0.5v, shutting off the switch and reducing the power. the output capacitor and the in- ductor supply the power to the load until ith rises above approximately 0.5v, turning on the switch and the main control loop which starts another cycle. for lower output voltage ripple at low currents, pulse skipping mode can be used. in this mode, the ltc3565 continues to switch at a constant frequency down to very low currents, where it will eventually begin skipping pulses. finally, in forced continuous mode, the inductor current is constantly cycled which creates a ? xed output voltage ripple at all output current levels. this feature is desirable in telecommunications since the noise is at a constant fre- quency and is thus easy to ? lter out. another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking current from the output. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. low supply operation the ltc3565 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 1.9v to prevent unstable operation.
ltc3565 10 3565fb applications information a general ltc3565 application circuit is shown in figure 4. external component selection is driven by the load requirement, and begins with the selection of the induc- tor l1. once l1 is chosen, c in and c out can be selected. operating frequency selection of the operating frequency is a trade-off between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f o , of the ltc3565 is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r t = 1.21 10 6 (f o ) C1.2674 (k) where r t is in k and f o is in khz or can be selected us- ing figure 1. the maximum usable operating frequency is limited by the minimum on-time and the duty cycle. this can be calculated as: f o(max ) 6.67 ? v out v in(max) (mhz) the minimum frequency is limited by leakage and noise coupling due to the large resistance of r t . inductor selection the operating frequency, f o , has a direct effect on the inductor value, which in turn in? uences the inductor ripple current, i l : i l = v out f o ?l ?1 ? v out v in ? ? ? ? ? ? the inductor ripple current decreases with larger induc- tance or frequency, and increases with higher v in or v out . accepting larger values of i l allows the use of lower inductances, but results in higher output ripple voltage, greater core loss and lower output capability. a reasonable starting point for setting ripple current is i l = 0.4 ? i out(max) , where i out(max) is 1.25a. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l = v out f o ? i l ?1 ? v out v in(max) ? ? ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower induc- tance values will cause the burst frequency to increase. figure 1. frequency vs r t inductor core selection different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated ? eld/emi requirements than on what the ltc3565 requires to operate. table 1 r t (k) 0 0 frequency (khz) 500 1500 2000 2500 5000 4500 3565 f01 1000 100 200 300 400 600500 3000 3500 4000 t a = 25c
ltc3565 11 3565fb applications information shows some typical surface mount inductors that work well in ltc3565 applications. table 1. representative surface mount inductors manu- facturer part number v alue max dc current dcr height toko a914byw-1r2m=p3: d52lc 1.2h 2.15a 44m 2mm a960aw-1r2m=p3: d518lc 1.2h 1.8a 46m 1.8mm db3015c-1068as-1r0n 1.0h 2.1a 43m 1.5mm db3018c-1069as-1r0n 1.0h 2.1a 45m 1.8mm db3020c-1070as-1r0n 1.0h 2.1a 47m 2mm a914byw-2r2m-d52lc 2.2h 2.05a 49m 2mm a915ay-2rom-d53lc 2.0h 3.3a 22m 3mm coilcraft lpo1704-122ml 1.2h 2.1a 80m 1mm d01608c-222 2.2h 2.3a 70m 3mm lp01704-222m 2.2h 2.4a 120m 1mm sumida cr32-1r0 1.0h 2.1a 72m 3mm cr5d11-1r0 1.0h 2.2a 40m 1.2mm cdrh3d14-1r2 1.2h 2.2a 36m 1.5mm cdrh4d18c/ld-1r1 1.1h 2.1a 24m 2mm cdrh4d28c/ld-1r0 1.0h 3.0a 17.5m 3mm cdrh4d28c-1r1 1.1h 3.8a 22m 3mm cdrh4d28-1r2 1.2h 2.56a 23.6m 3mm cdrh6d12-1r0 1.0h 2.80a 37.5m 1.5mm cdrh4d282r2 2.2h 2.04a 23m 3mm cdc5d232r2 2.2h 2.16a 30m 2.5mm taiyo yuden npo3sb1rom 1.0h 2.6a 27m 1.8mm n06db2r2m 2.2h 3.2a 29m 3.2mm n05db2r2m 2.2h 2.9a 32m 2.8mm murata lqn6c2r2m04 2.2h 3.2a 24m 5mm fdk mipw3226dorgm 0.9h 1.4a 80m 1mm catch diode selection although unnecessary in most applications, a small improvement in ef? ciency can be obtained in a few ap- plications by including the optional diode d1 shown in figure 2, which conducts when the synchronous switch is off. when using burst mode operation or pulse skip mode, the synchronous switch is turned off at a low current and the remaining current will be carried by the optional diode. it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. the main problem with schottky diodes is that their parasitic capacitance reduces the ef? ciency, usually negating the possible bene? ts for ltc3565 circuits. another problem that a schottky diode can introduce is higher leakage current at high tempera- tures, which could reduce the low current ef? ciency. remember to keep lead lengths short and observe proper grounding (see board layout considerations) to avoid ring- ing and increased dissipation when using a catch diode. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms i max v out (v in ? v out ) v in where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max ? i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case is commonly used to design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple cur- rent ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satis? ed, the capacitance
ltc3565 12 3565fb is adequate for ? ltering. the output ripple ( v out ) is determined by: v out ? i l esr + 1 8f o c out ? ? ? ? ? ? ? ? where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.4 ? i out(max) , the output ripple will be less than 100mv at maximum v in , a minimum c out of 10f and f o = 1mhz with: esrc out < 150m once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap , offer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it has a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signi? cantly larger esr, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost but also have the lowest capacitance density, a high voltage and temperature coef? cient and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to signi? cant ringing. other capacitor types include the panasonic specialty polymer (sp) capacitors. in most cases, 0.1f to 1f of ceramic capacitors should also be placed close to the ltc3565 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. because the ltc3565s control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. however, care must be taken when ceramic capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. refer to linear technology application note 88 for a detailed discussion of this potential issue. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead ful? ll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation com- ponents and the output capacitor value. typically, 3 to 4 cycles are required to respond to a load step, but only in the ? rst cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 3 times the linear applications information
ltc3565 13 3565fb drop of the ? rst cycle. thus, a good place to start is with the output capacitor value of approximately: c out 2.5 i out f o ?v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3565 develops a 0.6v reference voltage between the feedback pin, v fb , and the signal ground as shown in figure 4. the output voltage is set by a resistive divider according to the following formula: v out 0.6v 1 + r2 r1 ? ? ? ? ? ? keeping the current small (<5a) in these resistors maxi- mizes ef? ciency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward capaci- tor c f may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. shutdown and soft-start pulling the run pin high allows an internal soft-start circuit to slowly ramp the output voltage up until regulation. soft-start prevents surge currents from v in by gradually ramping the output voltage up during start-up. the output will ramp from zero to full scale over a time period of ap- proximately 0.9ms. this prevents the ltc3565 from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. the ltc3565 can start into a back-biased output in force continuous operation. when the output is pre-biased at either a higher or lower value than the regulated output voltage, the ltc3565 will sink or source current as needed to bring the output back into regulation. however, during soft-start the regulator will always start in pulse skip mode ignoring the mode selected with the sync/mode pin. this prevents the output from discharging to below the regulation point when soft-starting. mode selection and frequency synchronization the sync/mode pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation, which provides the best low current ef? ciency at the cost of a higher output voltage ripple. when this pin is connected to ground, pulse skipping operation is selected which provides the lowest output voltage and current ripple at the cost of low current ef? ciency. applying a voltage that is half the value of the input voltage results in forced continuous mode, which creates a ? xed output ripple and is capable of sinking up to 0.4a. since the switching noise is constant in this mode, it is also the easiest to ? lter out. the ltc3565 can also be synchronized to an external clock signal by the sync/mode pin. the internal oscilla- tor frequency should be set to 20% of the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. during synchronization, the mode is set to pulse skipping and the top switch turn on is synchronized to the falling edge of the external clock. applications information
ltc3565 14 3565fb checking transient response the opti-loop ? compensation allows the transient re- sponse to be optimized for a wide range of loads and output capacitors. the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc coupled and ac ? ltered closed loop response test point. the dc step, rise time and settling time at this test point truly re? ects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in the circuit on page 1 of this data sheet will provide an adequate starting point for most applications. the series r-c ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generat- ing a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with r and the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor c f can be added to improve the high frequency response, as shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. applications information pv in ltc3565 pgood pgood sw sv in sync/mode run v fb ith rt l1 d1 optional v in gnd r5 c f r t r c r1 r2 3565 f04 c c c ith c5 v out c in + + c6 c out r6 c8 figure 2. ltc3565 general schematic
ltc3565 15 3565fb although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage v in drops toward v out , the load step capability does decrease due to the decreasing voltage across the inductor. applications that require large load step capabil- ity near dropout should use a different topology such as sepic, zeta or single inductor, positive buck/boost. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed speci? cally for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: %ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3565 circuits: 1) ltc3565 v in current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continu- ous mode, i gatechg = f o (qt + qb), where qt and qb are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? owing through inductor l is chopped between the internal top and bottom switches. thus, the series resistance look- ing into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2(r sw + r l ) 4) other hidden losses such as copper trace and internal battery resistances can account for additional ef? ciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. other applications information figure 3. power loss vs load currrent load current (ma) v out = 1.2v v out = 1.5v v out = 1.8v 0.0001 power loss (w) 0.001 1 0.1 1 10 100 1000 10000 3565 f05 0.01 0.1 v in = 3.6v f o = 1mhz v out = 1.2v - 1.8v
ltc3565 16 3565fb applications information losses including diode conduction losses during dead-time and inductor core losses, which generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3565 does not dis- sipate much heat due to its high ef? ciency. however, in applications where the ltc3565 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3565 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3565 is in dropout at an input voltage of 3.3v with a load current of 1a. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the p-channel switch is 0.160. therefore, power dissipated by the part is: p d = i out 2 ? r ds(on) = 160mw the mse package junction-to-ambient thermal resistance, ja , will be in the range of about 40c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.16 ? 40 + 70 = 76.4c remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. however, we can safely as- sume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125c. design example as a design example, consider using the ltc3565 in a portable application with a li-ion battery. the battery pro- vides a v in = 2.5v to 4.2v. the load requires a maximum of 1.25a in active mode and 10ma in standby mode. the output voltage is v out = 2.5v. since the load still needs power in standby, burst mode operation is selected for good low load ef? ciency. first, calculate the timing resistor for 1mhz operation: r t = 1.21 ? 10 6 (10 3 ) C1.2674 = 190.8k use a standard value of 191k. next, calculate the inductor value for about 40% ripple current at maximum v in : l = 2.5v 1mhz ? 500ma ?1 ? 2.5v 4.2v ? ? ? ? ? ? = 2h choosing the closest inductor from a vendor of 2.2h, results in a maximum ripple current of: i l = 2.5v 1mhz ? 2.2h ?1 ? 2.5v 4.2v ? ? ? ? ? ? = 460ma for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c out 2.5 1.25a 1mhz ?(5% ? 2.5v) = 25f the closest standard value is 22f. since the output impedance of a li-ion battery is very low, c in is typically 22f. in noisy environments, decoupling sv in from pv in with an r6/c8 ? lter of 1/0.1f may help, but is typically not needed.
ltc3565 17 3565fb applications information the output voltage can now be programmed by choosing the values of r1 and r2. to maintain high ef? ciency, the current in these resistors should be kept small. choosing 2a with the 0.6v feedback voltage makes r1~300k. a close standard 1% resistor value is 294k then r2 is 931k. the compensation should be optimized for these compo- nents by examining the load step response but a good place to start for the ltc3565 is with a 12.1k and 680pf ? lter. the output capacitor may need to be increased depending on the actual undershoot during a load step. the pgood pin is a common drain output and requires a pull- up resistor. a 100k resistor is used for adequate speed. the circuit on page 1 of this data sheet shows the complete schematic for this design example. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3565. these items are also illustrated graphically in the layout diagram of figure 4. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 6) and power gnd (pin 5) as close as possible? this capacitor provides the ac current to the internal power mosfets and their drivers. 2. are the c out and l1 closely connected? the (C) plate of c out returns current to pgnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out and a ground line. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line (pin 4), and its trace should be minimized. 4. keep sensitive components away from the sw pin. the input capacitor c in , the compensation capacitor c c and c ith and all the resistors r1, r2, r t , and r c should be routed away from the sw trace and the inductor l1. the sw pin pad should be kept as small as possible. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at one point. 6. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. these copper areas should be connected to one of the input supply rails: pv in , sv in or gnd. l1 1 2 3 4 5 10 9 8 7 6 c c c ith c4 3565 f06 r c r1 r2 v in v out bold lines indicate high current paths c in c out pv in ltc3565 gnd sw sv in sync/mode pgood v fb r5 run ith rt r t figure 4. ltc3565 layout diagram (see board layout checklist)
ltc3565 18 3565fb sv in ltc3565 pgood pgood sw pv in sync/mode v fb ith shdn/rt l1 2.2h v in 2.5v to 5.5v v out 1.8v/1.5v/1.2v at 1.25a r5 100k r4 191k r1a 147k r3 12.1k rs1 1m bm rs2 1m 3565 ta02a c3 680pf c4 22pf r2 294k c2 22f r1b 196k r1c 294k ps fc c1 22f gnd note: in dropout, the output tracks the input voltage c1, c2: t aiyo yuden jmk325bj226mm l1: toko a914byw-2r2m (d52lc series) 1.8v 1.5v 1.2v general purpose buck regulator using ceramic capacitors ef? ciency vs output current typical application output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 1000 10000 3565 ta02b burst mode operation v in = 3.6v v out = 1.2v f o = 1mhz forced continuous pulse skip v in = 3.6v v out = 1.2v i load = 100ma to 1.25a burst mode operation v out 100mv/div ac coupled i l 1a/div 3565 ta02c 40s/div i load 1a/div v in = 3.6v v out = 1.8v i load = 100ma to 1.25a pulse skipping mode v out 100mv/div ac coupled i l 1a/div 3565 ta02d 40s/div i load 1a/div
ltc3565 19 3565fb package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer
ltc3565 20 3565fb package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse) 0911 rev h 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev h)
ltc3565 21 3565fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 2/10 changes to electrical characteristics change t a = 25c to t j = 25c changes to pin functions (gnd pin 5) changes to block diagram updated related parts table 2, 3 2, 3, 4, 5, 6 8 9 20 b 03/12 changed top marking for dfn package clari? ed temperature grade test conditions added note for website referral for most recent package drawings 2 3 20
ltc3565 22 3565fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0312 rev b ? printed in usa related parts part number description comments LTC3406/LTC3406b 600ma (i out ), 1.5mhz synchronous step-down dc/dc converters 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd < 1a, thinsot? ltc3407a/ltc3407ab dual 600ma/800ma (i out ), 1.5mhz/2.25mhz synchronous step-down dc/dc converters 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, ms10e, dfn ltc3410/ltc3410b 300ma (i out ), 2.25mhz synchronous step-down dc/dc converters 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26a, i sd < 1a, sc70 ltc3411a 1.25a (i out ), 4mhz synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, ms10, 3mm 3mm dfn ltc3412a 3a (i out ), 4mhz synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 62a, i sd < 1a, tssop16e, 4mm 4mm qfn ltc3560 800ma (i out ), 2.25mhz synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 16a, i sd < 1a, thinsot typical application 1mm height, 2mhz, li-ion to 1.8v converter output current (ma) 0.1 1 10 0 efficiency (%) 40 30 100 1000 100 10000 3565 ta04b 20 10 60 50 80 70 90 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.8v f o = 2mhz v in = 3.6v v out = 1.8v i load = 50ma to 1.25a v out 100mv/div ac coupled i l 1a/div i load 1a/div 3565 ta04c 40s/div v in = 3.6v v out = 1.8v i load = 250ma to 1.25a 3565 f04d 40s/div v out 100mv/div ac coupled i l 1a/div i load 1a/div ef? ciency vs output current pv in ltc3565 pgood pgood sw sv in run sync/mode v fb ith rt l1 0.9h v out 1.8v at 1.25a v in 2.5v to 4.2v gnd r5 100k c4, 22pf r4 80.6k r1 232k r2 464k 3565 ta04a r3 13.3k c3 470pf c2 10f 2 c1 10f c1, c2: taiyo yuden jmk107bj106ma l1: fdk mipw3226dorgm

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